![]() ![]() As time presses on though, users are likely abandoning these older GPUs in favor of newer parts. Now let's just hope that soft FP64 will make it into a Mesa 19.x release. So in the end these patches will help potentially shave off some memory usage by the NIR code employed by multiple Mesa/Gallium drivers and is a win particularly for the soft FP64 code. These memory usage improvements for NIR were uncovered as part of the soft FP64 work, as mentioned by the patches. Posted yesterday were a set of seven patches by Intel's Ian Romanick for reducing worst-case memory usage in NIR. It looks like some work is still quietly progressing on the soft FP64 front. This FP64 emulation support will also help out older Intel and NVIDIA (via Nouveau) GPUs as well that lack native hardware double precision floating point capabilities. ![]() It's been a while since any exciting soft FP64 work was presented, but this work is notable in it will let AMD Evergreen GPUs expose OpenGL 4.3 with the open-source driver stack. While we haven't seen any new soft FP64 patches in a while, not all hope is lost. Another unfortunate feature not making it into the Mesa 18.x release series is the "soft FP64" support to allow some older GPUs to work with OpenGL 4.x. assembly operations to convert 6+10 format to IEEE-754 FP32 or FP64. To build it you'll need CL_VERSION_1_2 headers.When it comes to letdowns for Mesa in 2018, sadly OpenGL 4.6 support didn't reach mainline. Values are strictly positive no sign bit needed. Supplied build script is for linux and osx, but building it for windows should be trivial. Code size overhead for a full SW emulation library The FPUs need just the functions to emulate fdivand fsqrton the integer datapath Code size overhead up to 80 smaller when implementing Tiny-FPU -79 -80 14 Information Classification: General Results - Performance High FP Snitch-tinyup to 18.5x(DP) and 15. In case somebody feel adventurous, here's a CLI tool which will report the double caps as well (AMD's clinfo currently does not). Platform Extensions: cl_khr_icd cl_amd_event_callback cl_amd_offline_devices cl_khr_d3d10_sharingĮxtensions: cl_khr_fp64 cl_amd_fp64 cl_khr_global_int32_base_atomics cl_khr_global_int32_extended_atomics cl_khr_local_int32_base_atomics cl_khr_local_int32_extended_atomics cl_khr_3d_image_writes cl_khr_byte_addressable_store cl_khr_gl_sharing cl_ext_atomic_counters_32 cl_amd_device_attribute_query cl_amd_vec3 cl_amd_printf cl_amd_media_ops cl_amd_popcnt cl_khr_d3d10_sharing cl_amd_meminfo Platform Version: OpenCL 1.1 AMD-APP (873.1) Name: Intel(R) Core(TM)2 Quad CPU Q6600 2.40GHzĮxtensions: cl_khr_fp64 cl_amd_fp64 cl_khr_global_int32_base_atomics cl_khr_global_int32_extended_atomics cl_khr_local_int32_base_atomics cl_khr_local_int32_extended_atomics cl_khr_3d_image_writes cl_khr_byte_addressable_store cl_khr_gl_sharing cl_ext_device_fission cl_amd_device_attribute_query cl_amd_vec3 cl_amd_printf cl_amd_media_ops cl_amd_media_ops2 cl_amd_popcnt cl_khr_d3d10_sharing Kernel Preferred work group size multiple: 1 Kernel Preferred work group size multiple: 64Įxtensions: cl_khr_fp64 cl_amd_fp64 cl_khr_global_int32_base_atomics cl_khr_global_int32_extended_atomics cl_khr_local_int32_base_atomics cl_khr_local_int32_extended_atomics cl_khr_3d_image_writes cl_khr_byte_addressable_store cl_khr_gl_sharing cl_ext_atomic_counters_32 cl_amd_device_attribute_query cl_amd_vec3 cl_amd_printf cl_amd_media_ops cl_amd_media_ops2 cl_amd_popcnt cl_khr_d3d10_sharing The comparison should be straightforward using a lexicographic ordering. Since double-float operations also increase register pressure compared with double, an overall estimate of double-float executing at 1/20 the speed of native IEEE-754 float seems reasonably conservative. ![]() So a double d will be emulated as a struct containing the tuple: (float d.hi, float d.low). Effective accuracy is around 44 bits vs 53 for double. I am trying to emulate double datatype using a tuple of two float s. Single precision floating point capability The algorithm I am implementing, however, requires a 64-bit double-precision addition and comparison. Minimum alignment (bytes) for any datatype: 128 Platform Extensions: cl_khr_icd cl_amd_event_callback cl_amd_offline_devices cl_khr_d3d10_sharing cl_khr_d3d11_sharing The patches up for testing can be found on Mesa-dev. GLARBshaderfp64 is mandated for OpenGL 4.0. Platform Vendor: Advanced Micro Devices, Inc. With a set of 11 patches posted today that amount to over 25 thousand lines of new code, GLARBshaderfp64 support can be exposed for all OpenGL 3.0 GPUs by doing the FP64 operations with pure GLSL. Platform Name: AMD Accelerated Parallel Processing Platform Version: OpenCL 1.2 AMD-APP (1124.2) ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |